This application claims priority from Korean Patent Application No. 2002-53329, filed on Sep. 4, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and more particularly, to a full CMOS SRAM device having 6 transistors formed on a silicon-on-insulator (SOI) substrate.
2. Description of the Related Art
Semiconductor memory devices are classified into dynamic random access memories (DRAMs), non-volatile memories, and SRAMs according to the manner in which data is stored. SRAMs offer the advantage of fast operating speeds in a simple manner with low power consumption. Also, in contrast with DRAMs, since SRAMs do not need to refresh periodically-stored information, design and manufacture are relatively easy.
In general, SRAM cells are comprised of two drive transistors, two load devices, and two access transistors. SRAMs can in turn be classified into full CMOS SRAMs, high load resistor (HLR) SRAMs, and thin film transistor (TFT) SRAMs according to the type of load devices included. Full CMOS SRAMs use PMOS transistors as load devices, HLR SRAMs use HLRs as load devices, and TFT SRAMs use polysilicon TFTs as load devices.
A conventional full CMOS SRAM circuit is shown in FIG. 1. As shown in FIG. 1, a full CMOS SRAM includes first and second inverters INV1 and INV2, which form a latch, and access transistors TA1 and TA2 for selectively driving the first and second inverters INV1 and INV2.
The first inverter INV1 includes a first PMOS transistor TP1 and a first NMOS transistor TN1, and the second inverter INV2 includes a second PMOS transistor TP2 and a second NMOS transistor TN2. The source of each of the first and second PMOS transistors TP1 and TP2 is coupled to a voltage terminal Vdd. The drain of the first PMOS transistor TP1 is coupled to that of the first NMOS transistor TN1, while the drain of the second PMOS transistor TP2 is coupled to that of the second NMOS transistor TN2. The source of each of the first and second NMOS transistors TN1 and TN2 is coupled to a ground voltage terminal Vss. The gate of the first PMOS transistor TP1 is coupled to that of the first NMOS transistor TN1, and the two gates are coupled to the output terminal S2 of the second inverter INV2, that is, to a common drain between the second PMOS transistor TP2 and the second NMOS transistor TN2. The gate of the second PMOS transistor TP2 is coupled to that of the second NMOS transistor TN2, and the two gates are coupled to the output terminal S1 of the first inverter INV1, that is, to a common drain between the first PMOS transistor TP1 and the first NMOS transistor TN1.
The gate of the first access transistor TA1 is coupled to a word line WL, its source is coupled to a bit line BL, and its drain is coupled to the output terminal S1 of the first inverter INV1. Similarly, the gate of the second access transistor TA2 is coupled to the word line WL, its source is coupled to a bit line bar DBL, and its drain is coupled to the output terminal S2 of the second inverter INV2. Here, the bit line bar DBL line carries the inverted BL signal.
In the operation of the above-described full CMOS SRAM device, if the potential of the word line WL is high, the first and second access transistors TA1 and TA2 are turned on, and accordingly, the signals of the bit line BL and bit line bar DBL are transmitted to the first and second inverters INV1 and INV2, respectively. Accordingly, data writing or reading is performed.
A conventional CMOS SRAM having such a structure is integrated into a bulk silicon substrate having the layout shown in FIG. 2. FIG. 2 shows only an active area of an SRAM, a gate electrode (word line), and a contacting portion.
As shown in FIG. 2, an isolation film 15 is formed on a silicon semiconductor substrate 10 so as to define a NMOS transistor active area 30 and a PMOS transistor active area 50. The NMOS transistor active area 30 may have a P well, and is formed in, for example, a “U” shape. Hereinafter, both sidewalls of the “U” shape are referred to as vertical portions, and a portion connecting the vertical portions is referred to as a horizontal portion. The PMOS transistor active area 50 may have an N-well, and is formed in, for example, a bar shape.
The word line WL extends so as to cross a predetermined portion of the NMOS transistor active area 30, for example, both vertical portions of the NMOS transistor active area 30, at a right angle. First and second gate electrodes 60 and 65 are disposed so as to pass between the horizontal portion of the NMOS transistor active area 30 and a predetermined portion of the PMOS transistor active area 50. Here, the first and second gate electrodes 60 and 65 may be perpendicular to the word line WL. The first gate electrode 60 serves as the gate electrodes of the first NMOS transistor TN1 and the first PMOS transistor TP1, and the second gate electrode 65 serves as the gate electrodes of the second NMOS transistor TN2 and the second PMOS transistor TP2.
N-type impurities are implanted into the word line WL and a portion of the NMOS transistor active area 30 on the outer sides of the gate electrodes 60 and 65, so that the first and second access transistors TA1 and TA2 and the first and second NMOS transistors TN1 and TN2 are formed. P-type impurities are implanted into a portion of the PMOS transistor active area 50 on the outer sides of the gate electrodes 60 and 65 so that the first and second PMOS transistors TP1 and TP2 are formed.
In FIG. 2, reference character BLC denotes a contact area where the source of the first access transistor TA1 contacts a bit line BL, and reference character DBLC denotes a contact area where the source of the second access transistor TA2 contacts a bit line bar DBL. Reference characters S1, S1′, S2, and S2′ denote the output portions of the inverters INV1 and INV2. Although S1 and S1′ are isolated from each other and S2 and S2′ are isolated from each other, S1 and S2 will be coupled to S1′ and S2′, respectively, during wiring. Reference character Vdd denotes an area for contact with a Vdd line (not shown), reference character Vss denotes an area for contact with a Vss line (not shown), and reference character GC denotes an area where a gate electrode is to contact a gate power line (not shown) later.
However, when the conventional full CMOS SRAM is formed on a bulk silicon substrate, the following problems are generated. As shown in FIG. 2, since the conventional full CMOS SRAM includes a PMOS transistor and an NMOS transistor at the same time, a P-well active area for the NMOS transistor and an N-well active area for the PMOS transistor are needed. However, as well known, when an N well and a P well are disposed adjacent to each other, a parasitic bipolar transistor that creates a phenomenon referred to as “latch-up” may be formed. Hence, the P well must be isolated from the N well by a predetermined distance (A), that is, a distance great enough to prevent a latch-up from being formed. This distance (A) between the P well and the N well contributes to an increase in the chip size of an SRAM.
Also, since a PMOS transistor has a much slower mobility than the mobility of an NMOS transistor, the PMOS transistor must be larger than the NMOS transistor in order to provide for stable operation. Therefore, conventional full CMOS SRAMs having PMOS transistors are larger than SRAMs having no PMOS transistors.